Behavior of Self Timed Null Convention Logic Circuits with Threshold Variations

Due to increasing overheads, it is more and more difficult for the clocked architectures to fulfill design challenges like high performance, complexity, ease of design reuse. To overcome these clocked issues, clock-less asynchronous design paradigms such as the NULL Convention Logic (NCL) is used. NCL is sine qua non in future semiconductor paradigms to face new design challenges. Several researches have proved that NCL has significant improvements such as power reduction and more robust to noise when compared to clocked architectures. In this paper, we incorporate power reduction technique, Multi-Threshold CMOS (MTCMOS) to delayinsensitive self-timed NCL so called Multi-Threshold NULL Convention Logic (MTNCL) that can significantly reduce leakage power and improve performance. Quantitative analysis has been performed and compared with static CMOS, MTCMOS and NCL on Tanner EDA tools. Results show that the proposed MTNCL technique significantly reduces power when compared to all the other static designs.